Built-in real-time digital non-linearity measurement device and method for analog to digital converters

ABSTRACT

A nonlinearity detection system for an analog to digital converter (ADC) comprises a signal generator that generates a periodic signal that is output to the ADC and that comprises first and second intervals. The periodic signal monotonically increases during the first interval and monotonically decreases during the second interval. A differentiator module communicates with the ADC and that generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.10/795,907 filed on Mar. 8, 2004 now U.S. Pat. No. 6,943,712 and claimsthe benefit of U.S. Provisional Application No. 60/517,722, filed onNov. 6, 2003, which are hereby incorporated by reference in theirentirety.

FIELD OF THE INVENTION

The present invention relates to analog to digital converters (ADCs),and more particularly to digital non-linearity measurement devices andmethods for ADCs.

BACKGROUND OF THE INVENTION

Analog to digital converters (ADCs) convert an analog input signal to adigital output signal. ADCs are typically implemented on an integratedcircuit (IC) or chip. The output of the ADCs typically containnonlinearity errors that need to be characterized. The nonlinearityerrors may occur when the ADC has a higher gain than expected duringdesign, a lower gain than expected during design, multiple inputvoltages having the same output code, and/or in other situations.

In one conventional approach for characterizing the nonlinearity of theADC, a tone is applied to an input of ADC. Tones are sinusoidal signalshaving a fixed frequency. Referring now to FIG. 1, a test signalgenerator 10 outputs the tone to an input of an ADC 14. An output of theADC 14 is input to a nonlinearity detector 18. The nonlinearity detector18 is typically an off-chip device that uses conventional algorithmsthat detect nonlinearities in the output of the ADC 14. Time consumingpost-processing must be performed to characterize the nonlinearity ofthe ADC 14. The post-processing is repeated for different operatingconditions such as but not limited to temperature, which increases thecharacterization time. In some circumstances, it may take on the orderof days to properly characterize the ADC 14.

SUMMARY OF THE INVENTION

A nonlinearity detection system for an analog to digital converter (ADC)comprises a signal generator that generates a periodic signal that isoutput to the ADC and that comprises first and second intervals. Thesaid periodic signal monotonically increases during the first intervaland monotonically decreases during the second interval. A differentiatormodule communicates with the ADC and generates an output signal that isbased on an output of the ADC and a delayed output of the ADC. Anonlinearity detection module detects slope discontinuities in theoutput signal of the differentiator module.

Further areas of applicability of the present invention will becomeapparent from the detailed description provided hereinafter. It shouldbe understood that the detailed description and specific examples, whileindicating the preferred embodiment of the invention, are intended forpurposes of illustration only and are not intended to limit the scope ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description and the accompanying drawings, wherein:

FIG. 1 is a functional block diagram of a nonlinearity detectoraccording to the prior art;

FIG. 2A is a functional block diagram of a nonlinearity detection moduleaccording to the present invention;

FIG. 2B is a functional block diagram of an exemplary differentiatormodule;

FIG. 2C is a functional block diagram of one exemplary implementation ofthe nonlinearity detection module according to the present invention;

FIG. 3 are waveforms illustrating the input voltage, output voltage anddifferentiator module output according to the present invention;

FIG. 4 is a waveform illustrating positive and negative maximum andminimum slope ranges of the differentiator module output;

FIGS. 5A and 5B are waveforms illustrating the output voltage of ADC andthe output of the differentiator module, respectively, when the gain ofthe ADC is greater than expected;

FIGS. 6A and 6B are waveforms illustrating the output voltage of ADC andthe output of the differentiator module, respectively, when the gain ofthe ADC is less than expected;

FIGS. 7A and 7B are waveforms illustrating the output voltage of ADC andthe output of the differentiator module, respectively, when certainranges of the ADC have the same output codes;

FIG. 8 is a flowchart illustrating steps for characterizing thenonlinearity of the ADC;

FIG. 9 is a flowchart illustrating steps for detecting discontinuitiesin the positive and negative slope regions of the ADC;

FIG. 10 is a state diagram for an exemplary implementation of thenonlinearity detection module; and

FIG. 11 is a functional block diagram of a network device that includesa physical layer module with nonlinearity detection module.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description of the preferred embodiment(s) is merelyexemplary in nature and is in no way intended to limit the invention,its application, or uses. For purposes of clarity, the same referencenumbers will be used in the drawings to identify similar elements. Asused herein, the term module refers to an application specificintegrated circuit (ASIC), an electronic circuit, a processor (shared,dedicated, or group) and memory that execute one or more software orfirmware programs, a combinational logic circuit, and/or other suitablecomponents that provide the described functionality.

Referring now to FIGS. 2A and 2B, a triangle wave generator 50 outputs atriangular wave V_(in) to an input of the ADC 14. The triangular waveV_(in) has alternating regions with positive and negative slopes. Theoutput signal V_(out) of the ADC 14 is input to a differentiator module54. The differentiator module 54 generates an output signal that isbiased on V_(out) and a delayed V_(out). The output of thedifferentiator module 54 is input to a nonlinearity detection module 58,which generates a nonlinearity test pass/fail signal as will bedescribed in further detail below.

In one implementation, the differentiator module 54 includes a delayelement 59 and a summer 60. The delay element 59 outputs a delayedV_(out) to an input of the summer 60. Another input of the summer 60receives V_(out). The summer 60 outputs V_(1−D), which is V_(out) minusa delayed V_(out). The differentiator module 54 can be a discrete timedifferentiator, a discrete time filter, a finite impulse response (FIR)filter and/or any other suitable circuit.

Referring now to FIG. 2C, one exemplary implementation of thenonlinearity detection module 58 according to the present invention isshown. A positive/negative slope module 61 identifies positive andnegative slope regions (after being differentiated) in the output of thedifferentiator module 54. A maximum/minimum positive slope limit module62 sets maximum and minimum positive slope limits. A maximum/minimumnegative slope limit module 64 sets maximum and minimum negative slopelimits. A comparing module 66 compares the output of the differentiatormodule 54 to either the maximum/minimum positive slope limits when thepositive slope region occurs or the maximum/minimum negative slopelimits when the negative slope region occurs. If the slope values do notfall within the respective limits, the comparing module 66 of thenonlinearity detection module 58 generates a nonlinearity test failsignal. If the slope values fall within the respective limits, thecomparing module 66 of the nonlinearity detection module 58 generates anonlinearity test pass signal. As can be appreciated, the nonlinearitytesting components can be implemented on-chip with the ADC 14.

Referring now to FIG. 3, the input signal V_(in), the output signalV_(out) and the output of the differentiator module V_(1−D) are shown at70, 72, and 74, respectively. In an ideal ADC, if a triangular waveformis input to an ADC, the output of the ADC is linear and has a constantslope between clipped regions 75-1 and 75-2 as shown. If the differencebetween the current ADC output and the previous ADC output (V_(1−D)) isplotted, the waveform has three major flat regions: maximum, 0, andminimum. The maximum and minimum values of V_(1−D) correspond to thepositive and negative slope regions of the rise and fall, respectively.

Referring now to FIG. 4, since ADCs are neither ideal nor perfectlylinear, the maximum and minimum regions of V_(1−D) will have a narrowrange of values rather than the single value that is shown in FIG. 3. Inother words, the positive slope will fall between a positive maximumslope value and a positive minimum slope value. The negative slope willfall between a negative minimum slope value and a negative maximum slopevalue. These expected values are used to set the limits of the limitmodules 62 and 64. The limit values that are selected will be based onthe anticipated linearity of the ADC and the desired sensitivity of thenonlinearity test.

Referring now to FIGS. 5A and 5B, if the gain of the ADC 14 is greaterthan expected during design, the output voltage of the ADC 14 willinclude non-uniform positive and/or negative slope regions 76 and 78.These non-uniform positive and/or negative slope regions will causediscontinuities or spikes 80 and 82, respectively, in the output of thedifferentiator module 54. The discontinuities or spikes 80 and 82represent nonlinearities in the output of the ADC 14.

Referring now to FIGS. 6A and 6B, if the gain of the ADC 14 is less thanexpected during design, the output voltage of the ADC 14 will includenon-uniform positive and/or negative slope regions 88 and 92,respectively. These non-uniform positive and/or negative slope regions88 and 92 will cause discontinuities or spikes 94 and 96, respectivelyin the output of the differentiator module 54. The discontinuities orspikes 94 and 96 fall outside of the respective positive and negativeminimum and maximum limits and represent nonlinearities in the output ofthe ADC 14.

Referring now to FIGS. 7A and 7B, if the ADC 14 outputs the same outputcode for certain input voltage regions, the output voltage of the ADC 14will include non-uniform positive and/or negative slope regions 100 and102. These non-uniform positive and/or negative slope regions 100 and102 will cause discontinuities or spikes 106 and 108, respectively, inthe output of the differentiator module 54. The discontinuities orspikes 106 and 108 represent nonlinearities in the output of the ADC 14.

Referring now to FIG. 8, steps for operating the nonlinearity detectorfor the ADC 14 are shown. In step 150, a triangular wave is output tothe ADC 14. In step 152, the output of the ADC 14 is differentiated. Instep 156, the nonlinearity detection module 58 monitors discontinuitiesor spikes in the output of the differentiator module 54. In step 160,control determines whether the discontinuities or spikes are detected.If not, the ADC 14 passes the test in step 164. Otherwise, the ADC 14fails the test in step 166.

Referring now to FIG. 9, simplified steps for detecting discontinuitiesor spikes are shown. In step 200, control determines whether there is apositive slope region. If true, control determines whether the positiveslope of the positive slope region is less than a positive maximum slopevalue and greater than a minimum positive slope value in step 204. Ifstep 204 is false, control detects a discontinuity in step 205 andcontrol returns in step 206. If step 204 is true, control determineswhether the positive slope region ended in step 208.

If step 208 is true, control continues with step 204. If step 208 isfalse, control continues with step 210 and determines whether the testis over. If step 210 is true, control returns in step 206. If step 210is false, control continues with step 200. If step 200 is false, controlcontinues with step 220 and determines whether there is a negative sloperegion. If step 220 is false, control continues with step 200. If step220 is true, control continues with step 224 and determines whether thenegative slope is greater than a negative slope maximum value and lessthan a negative slope minimum value. If step 224 is true, controldetermines whether the output of the ADC is still in the negative sloperegion in step 226. If step 226 is true, control continues with step224. If step 226 is false, control continues with step 210. If step 224is false, control detects a discontinuity in step 205 and controlreturns in step 206.

Referring now to FIG. 10, a nonlinearity test state machine 248 for anexemplary 9-bit ADC is shown. As can be appreciated, while FIG. 10describes a 9-bit ADC, the ADC can be any n-bit ADC, where n is aninteger. Variables used therein are defined as follows: count_(—)0 is acount of consecutive lowest ADC code, usually code 0. Count_(—)511 is acount of consecutive highest ADC code. ADC code 511 represents thehighest code output (when 9 bit ADCs are used). As can be appreciated,ADCs with other bit lengths will have codes will have a code of(2^(n)−1). psl_max is a maximum slope for positive slope regions.psl_min is a minimum slope for positive slope regions. nsl_max is amaximum slope for negative slope regions. nsl_min is a minimum slope fornegative slope regions.

When an enable signal is equal to zero, the state machine 248 goes to aRESET state 250. In the RESET state 250, variables are initialized asshown. When the enable signal is asserted, the state machine 248 movesto a WAIT state 254. In the WAIT state 254, it aligns to either the clipwaveform region where the ADC code equals 0 (clip region 0) or the clipwaveform region where the ADC code equals 511 (clip region 511).Variables count_(—)0 and count_(—)511 count the number of consecutiveADC codes equal to 0 or 511, respectively. When count_(—)0 orcount_(—)511 reaches a count threshold, the waveform is either in clipregion 0 or clip region 511. When a different ADC code is encounteredafter the count threshold has been reached, the state machine 248 movesto either 0_(—)511_skip state 258 or 511_(—)0_skip state 262. In eitherof the states 258 or 262, the slope based on this ADC 14 is not includedin the calculation of the maximum and minimum slopes. In the next cycle,the state machine 248 moves to either 0_(—)511 state 264 or 511 _(—)0state 268, respectively, where the maximum and minimum slopes arecalculated based on the following equations:

-   if((state == 0_(—)511) & ˜((ADC==0) & (prev_ADC==0)) & ˜((ADC==511)    & (prev_ADC==511)))    -   begin    -   (delta > psl_max) ? (psl_max = delta) : psl_max    -   (ADC!=511) & (delta < psl_min)(psl_min=delta) : psl_min    -   end-   if((state==511_(—)0) & ˜((ADC==0) & (prev_ADC==0)) & ˜((ADC==511) &    (prev_ADC==511)))    -   (delta < nsl_min) ? (nsl_min = delta) : nsl_min    -   (ADC!=0) & (delta > nsl_max) (nsl_max=delta) : nsl_max    -   end

Referring now to FIG. 11, a network device 310 is shown that includes aphysical layer module 314, which includes the triangle wave generator50, the ADC 14, the differentiator module 54, and the non-linearitydetection module 58. The physical layer module 314 communicates with amedium 315. In one embodiment, the medium 315 includes one or moretwisted pairs of wire, although other media may be used. The output ofthe non-linearity detection module 58 may be sent to one or more otherphysical layer circuits 318, to a medium access control (MAC) module 320and/or other layers 322.

The network device 310 can be an Ethernet network device that iswireless or wired. In one embodiment, the Ethernet network device is awired network that is compliant with 1000BaseT. Still otherimplementations will be apparent to skilled artisans.

Those skilled in the art can now appreciate from the foregoingdescription that the broad teachings of the present invention can beimplemented in a variety of forms. Therefore, while this invention hasbeen described in connection with particular examples thereof, the truescope of the invention should not be so limited since othermodifications will become apparent to the skilled practitioner upon astudy of the drawings, the specification and the following claims.

1. A nonlinearity detection system for an analog to digital converter(ADC), comprising: a signal generator that generates a periodic signalthat is output to the ADC and that comprises first and second intervals,wherein said periodic signal monotonically increases during said firstinterval and monotonically decreases during said second interval; adifferentiator module that communicates with the ADC and that generatesan output signal that is based on an output of the ADC and a delayedoutput of the ADC; and a nonlinearity detection module that detectsslope discontinuities in said output signal of said differentiatormodule.
 2. The nonlinearity detection system of claim 1 wherein saiddifferentiator module includes a discrete-time differentiator.
 3. Thenonlinearity detection system of claim 1 wherein said differentiatormodule includes a discrete time filter.
 4. The nonlinearity detectionsystem of claim 3 wherein said discrete time filter includes a finiteimpulse response (FIR) filter.
 5. An integrated circuit comprising thenonlinearity detection system of claim 1 and further comprising saidADC.
 6. The nonlinearity detection system of claim 1 wherein saidnonlinearity detection module determines maximum and minimum positiveand negative slope limits for positive and negative slope regions,respectively, of said output signal of said differentiator module. 7.The nonlinearity detection system of claim 6 wherein said nonlinearitydetection module compares slope values in said positive slope region tosaid maximum and minimum positive slope limits to detect said slopediscontinuities.
 8. The nonlinearity detection system of claim 7 whereinsaid nonlinearity detector generates a nonlinearity test fail signalwhen said slope values in said positive slope region are at least one ofgreater than said maximum positive slope limit and less than saidminimum positive slope limit during said positive slope regions.
 9. Thenonlinearity detection system of claim 6 wherein said nonlinearitydetection module compares slope values in said negative slope regions tosaid maximum and minimum negative slope limits to detect said slopediscontinuities.
 10. The nonlinearity detection system of claim 9wherein said nonlinearity detection module generates a nonlinearity testfail signal when said slope values in said negative slope regions are atleast one of greater than said maximum negative slope limit and lessthan said minimum negative slope limit during said negative sloperegions.
 11. The nonlinearity detection system of claim 1 wherein saidnonlinearity detection module comprises: a slope region identifyingmodule that identifies positive and negative slope regions in saidoutput signal of said differentiator module; a positive slope limitmodule that determines maximum and minimum limits for said positiveslope region; a negative slope limit module that determines maximum andminimum limits for said negative slope region; and a comparing modulethat receives said output signal of said differentiator module, thatcompares said output signal of said differentiator module to one of saidmaximum and minimum limits for said positive slope region and saidmaximum and minimum limits for said negative slope region, and thatgenerates a nonlinearity test signal based on said comparison.
 12. Thenonlinearity detection system of claim 7 wherein said nonlinearitydetector generates a nonlinearity test pass signal when said slopevalues in said positive slope region are at least one of less than saidmaximum positive slope limit and greater than said minimum positiveslope limit during said positive slope regions.
 13. The nonlinearitydetection system of claim 9 wherein said nonlinearity detection modulegenerates a nonlinearity test pass signal when said slope values in saidnegative slope regions are at least one of less than said maximumnegative slope limit and greater than said minimum negative slope limitduring said negative slope regions.
 14. An integrated circuit comprisingthe nonlinearity detection system of claim
 1. 15. An Ethernet physicallayer device comprising the nonlinearity detection system of claim 1.16. The Ethernet physical layer device of claim 15 wherein said Ethernetphysical layer device is compatible with 1000BaseT.
 17. A nonlinearitydetecting system for an analog to digital converter (ADC), comprising:signal generating means for generating a periodic signal that is outputto the ADC and that comprises first and second intervals, wherein saidperiodic signal monotonically increases during said first interval andmonotonically decreases during said second interval; differentiatingmeans that communicates with the ADC for generating an output signalthat is based on an output of the ADC and a delayed output of the ADC;and nonlinearity detecting means for detecting slope discontinuities insaid output signal of said differentiating means.
 18. The nonlinearitydetecting system of claim 17 wherein said differentiating means includesa discrete-time differentiator.
 19. The nonlinearity detecting system ofclaim 17 wherein said differentiating means includes a discrete timefilter.
 20. The nonlinearity detecting system of claim 19 wherein saiddiscrete time filter includes a finite impulse response (FIR) filter.21. An integrated circuit comprising the nonlinearity detecting systemof claim 17 and further comprising said ADC.
 22. The nonlinearitydetecting system of claim 17 wherein said nonlinearity detecting meansdetermines maximum and minimum positive and negative slope limits forpositive and negative slope regions, respectively, of said output signalof said differentiating means.
 23. The nonlinearity detecting system ofclaim 22 wherein said nonlinearity detecting means compares slope valuesin said positive slope region to said maximum and minimum positive slopelimits to detect said slope discontinuities.
 24. The nonlinearitydetecting system of claim 23 wherein said nonlinearity detecting meansgenerates a nonlinearity test fail signal when said slope values in saidpositive slope region are at least one of greater than said maximumpositive slope limit and less than said minimum positive slope limitduring said positive slope regions.
 25. The nonlinearity detectingsystem of claim 22 wherein said nonlinearity detecting means comparesslope values in said negative slope regions to said maximum and minimumnegative slope limits to detect said slope discontinuities.
 26. Thenonlinearity detecting system of claim 25 wherein said nonlinearitydetecting means generates a nonlinearity test fail signal when saidslope values in said negative slope regions are at least one of greaterthan said maximum negative slope limit and less than said minimumnegative slope limit during said negative slope regions.
 27. Thenonlinearity detecting system of claim 17 wherein said nonlinearitydetecting means comprises: slope region identifying means foridentifying positive and negative slope regions in said output signal ofsaid differentiating means; positive slope limit means for determiningmaximum and minimum limits for said positive slope region; negativeslope limit means for determining maximum and minimum limits for saidnegative slope region; and comparing means that receives said outputsignal of said differentiating means for comparing said output signal ofsaid differentiating means to one of said maximum and minimum limits forsaid positive slope region and said maximum and minimum limits for saidnegative slope region, and for generating a nonlinearity test signalbased on said comparison.
 28. The nonlinearity detecting system of claim23 wherein said nonlinearity detecting means generates a nonlinearitytest pass signal when said slope values in said positive slope regionare at least one of less than said maximum positive slope limit andgreater than said minimum positive slope limit during said positiveslope regions.
 29. The nonlinearity detecting system of claim 25 whereinsaid nonlinearity detecting means generates a nonlinearity test passsignal when said slope values in said negative slope regions are atleast one of less than said maximum negative slope limit and greaterthan said minimum negative slope limit during said negative sloperegions.
 30. An integrated circuit comprising the nonlinearity detectingsystem of claim
 17. 31. An Ethernet physical layer device comprising thenonlinearity detecting system of claim
 17. 32. The Ethernet physicallayer device of claim 31 wherein said Ehternet physical layer device iscompatible with 1000BaseT.
 33. A method for detecting nonlinearity in ananalog to digital converter (ADC), comprising: generating a periodicsignal that is output to the ADC and that comprises first and secondintervals, wherein said periodic signal monotonically increases duringsaid first interval and monotonically decreases during said secondinterval; generating an output signal that is based on an output of theADC and a delayed output of the ADC; and detecting slope discontinuitiesin said output signal.
 34. The method of claim 33 wherein said step ofgenerating said output signal includes performing discrete-timedifferentiation.
 35. The method of claim 33 wherein said step ofgenerating said output signal includes performing discrete timefiltering.
 36. The method of claim 35 wherein said discrete timefiltering includes finite impulse response (FIR) filtering.
 37. Themethod of claim 33 further comprising determining maximum and minimumpositive and negative slope limits for positive and negative sloperegions, respectively, of said output signal.
 38. The method of claim 37further comprising comparing slope values in said positive slope regionto said maximum and minimum positive slope limits to detect said slopediscontinuities.
 39. The method of claim 38 further comprisinggenerating a nonlinearity test fail signal when said slope values insaid positive slope region are at least one of greater than said maximumpositive slope limit and less than said minimum positive slope limitduring said positive slope regions.
 40. The method of claim 37 furthercomprising comparing slope values in said negative slope regions to saidmaximum and minimum negative slope limits to detect said slopediscontinuities.
 41. The method of claim 40 further comprisinggenerating a nonlinearity test fail signal when said slope values insaid negative slope regions are at least one of greater than saidmaximum negative slope limit and less than said minimum negative slopelimit during said negative slope regions.
 42. The method of claim 33further comprising: identifying positive and negative slope regions insaid output signal; determining maximum and minimum limits for saidpositive slope region; determining maximum and minimum limits for saidnegative slope region; comparing said output signal to one of saidmaximum and minimum limits for said positive slope region and saidmaximum and minimum limits for said negative slope region; andgenerating a nonlinearity test signal based on said comparison.
 43. Themethod of claim 40 further comprising generating a nonlinearity testpass signal when said slope values in said positive slope region are atleast one of less than said maximum positive slope limit and greaterthan said minimum positive slope limit during said positive sloperegions.
 44. The method of claim 40 further comprising generating anonlinearity test pass signal when said slope values in said negativeslope regions are at least one of less than said maximum negative slopelimit and greater than said minimum negative slope limit during saidnegative slope regions.